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Logical Effort in VLSI design and testing

This document discusses the concept of logical effort in CMOS VLSI design, which aids designers in optimizing circuit topology, stage count, and transistor sizes for performance. It includes examples of designing a decoder for a register file and the computation of delays in logic gates, emphasizing methods to minimize delay in multistage logic networks. The lecture underlines key results and calculations related to logical and electrical effort, parasitic delays, and presents various gate types along with their characteristics.

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Lecture 6: Logical Effort
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 2 Outline  Logical Effort  Delay in a Logic Gate  Multistage Logic Networks  Choosing the Best Number of Stages  Example  Summary
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 3 Introduction  Chip designers face a bewildering array of choices – What is the best circuit topology for a function? – How many stages of logic give least delay? – How wide should the transistors be?  Logical effort is a method to make these decisions – Uses a simple model of delay – Allows back-of-the-envelope calculations – Helps make rapid comparisons between alternatives – Emphasizes remarkable symmetries ? ? ?
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 4 Example  Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file.  Decoder specifications: – 16 word register file – Each word is 32 bits wide – Each bit presents load of 3 unit-sized transistors – True and complementary address inputs A[3:0] – Each input may drive 10 unit-sized transistors  Ben needs to decide: – How many stages to use? – How large should each gate be? – How fast can decoder operate? A[3:0] A[3:0] 16 32 bits 16 words 4:16 Decoder Register File
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 5 Delay in a Logic Gate  Express delays in process-independent unit  Delay has two components: d = f + p  f: effort delay = gh (a.k.a. stage effort) – Again has two components  g: logical effort – Measures relative ability of gate to deliver current – g  1 for inverter  h: electrical effort = Cout / Cin – Ratio of output to input capacitance – Sometimes called fanout  p: parasitic delay – Represents delay of gate driving no load – Set by internal parasitic capacitance abs d d   3RC  3 ps in 65 nm process 60 ps in 0.6 m process
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 6 Electrical Effort: h = Cout / Cin Normalized Delay: d Inverter 2-input NAND g = 1 p = 1 d = h + 1 g = 4/3 p = 2 d = (4/3)h + 2 Effort Delay: f Parasitic Delay: p 0 1 2 3 4 5 0 1 2 3 4 5 6 Electrical Effort: h = Cout / Cin Normalized Delay: d Inverter 2-input NAND g = p = d = g = p = d = 0 1 2 3 4 5 0 1 2 3 4 5 6 Delay Plots d = f + p = gh + p  What about NOR2?
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 7 Computing Logical Effort  DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.  Measure from delay vs. fanout plots  Or estimate by counting transistor widths A Y A B Y A B Y 1 2 1 1 2 2 2 2 4 4 Cin = 3 g = 3/3 Cin = 4 g = 4/3 Cin = 5 g = 5/3
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 8 Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 4/3 5/3 6/3 (n+2)/3 NOR 5/3 7/3 9/3 (2n+1)/3 Tristate / mux 2 2 2 2 2 XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8  Logical effort of common gates
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 9 Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 2 3 4 n NOR 2 3 4 n Tristate / mux 2 4 6 8 2n XOR, XNOR 4 6 8  Parasitic delay of common gates – In multiples of pinv (1)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 10 Example: Ring Oscillator  Estimate the frequency of an N-stage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay: d = 2 Frequency: fosc = 1/(2*N*d) = 1/4N 31 stage ring oscillator in 0.6 m process has frequency of ~ 200 MHz
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 11 Example: FO4 Inverter  Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay: d = 5 d The FO4 delay is about 300 ps in 0.6 m process 15 ps in a 65 nm process
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 12 Multistage Logic Networks  Logical effort generalizes to multistage networks  Path Logical Effort  Path Electrical Effort  Path Effort i G g  out-path in-path C H C  i i i F f g h     10 x y z 20 g1 = 1 h1 =x/10 g2 =5/3 h2 =y/x g3 =4/3 h3 =z/y g4 = 1 h4 =20/z
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 13 Multistage Logic Networks  Logical effort generalizes to multistage networks  Path Logical Effort  Path Electrical Effort  Path Effort  Can we write F = GH? i G g  out path in path C H C    i i i F f g h    
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 14 Paths that Branch  No! Consider paths that branch: G = 1 H = 90 / 5 = 18 GH = 18 h1 = (15 +15) / 5 = 6 h2 = 90 / 15 = 6 F = g1g2h1h2 = 36 = 2GH 5 15 15 90 90
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 15 Branching Effort  Introduce branching effort – Accounts for branching between stages in path  Now we compute the path effort – F = GBH on path off path on path C C b C   i B b  i h BH   Note:
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 16 Multistage Delays  Path Effort Delay  Path Parasitic Delay  Path Delay F i D f  i P p  i F D d D P    
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 17 Designing Fast Circuits  Delay is smallest when each stage bears same effort  Thus minimum delay of N stage path is  This is a key result of logical effort – Find fastest possible delay – Doesn’t require calculating gate sizes i F D d D P     1 ˆ N i i f g h F   1 N D NF P  
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 18 Gate Sizes  How wide should the gates be for least delay?  Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives.  Check work by verifying input cap spec is met. ˆ ˆ out in i i C C i out in f gh g g C C f    
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 19 Example: 3-stage path  Select gate sizes x and y for least delay from A to B 8 x x x y y 45 45 A B
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 20 Example: 3-stage path Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = 45/8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 Best Stage Effort Parasitic Delay P = 2 + 3 + 2 = 7 Delay D = 3*5 + 7 = 22 = 4.4 FO4 8 x x x y y 45 45 A B 3 ˆ 5 f F  
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 21 Example: 3-stage path  Work backward for sizes y = 45 * (5/3) / 5 = 15 x = (15*2) * (5/3) / 5 = 10 P: 4 N: 4 45 45 A B P: 4 N: 6 P: 12 N: 3 8 x x x y y 45 45 A B
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 22 Best Number of Stages  How many stages should a path use? – Minimizing number of stages is not always fastest  Example: drive 64-bit datapath with unit inverter D = NF1/N + P = N(64)1/N + N 1 1 1 1 8 4 16 8 2.8 23 64 64 64 64 Initial Driver Datapath Load N: f: D: 1 64 65 2 8 18 3 4 15 4 2.8 15.3 Fastest
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 23 Derivation  Consider adding inverters to end of path – How many give least delay?  Define best stage effort N - n1 ExtraInverters Logic Block: n1 Stages Path EffortF   1 1 1 1 N n i inv i D NF p N n p       1 1 1 ln 0 N N N inv D F F F p N         1 ln 0 inv p      1 N F  
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 24 Best Stage Effort  has no closed-form solution  Neglecting parasitics (pinv = 0), we find  = 2.718 (e)  For pinv = 1, solve numerically for  = 3.59   1 ln 0 inv p     
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 25 Sensitivity Analysis  How sensitive is delay to using exactly the best number of stages?  2.4 <  < 6 gives delay within 15% of optimal – We can be sloppy! – I like  = 4 1.0 1.2 1.4 1.6 1.0 2.0 0.5 1.4 0.7 N / N 1.15 1.26 1.51 ( =2.4) (=6) D(N) /D(N) 0.0
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 26 Example, Revisited  Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file.  Decoder specifications: – 16 word register file – Each word is 32 bits wide – Each bit presents load of 3 unit-sized transistors – True and complementary address inputs A[3:0] – Each input may drive 10 unit-sized transistors  Ben needs to decide: – How many stages to use? – How large should each gate be? – How fast can decoder operate? A[3:0] A[3:0] 16 32 bits 16 words 4:16 Decoder Register File
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 27 Number of Stages  Decoder effort is mainly electrical and branching Electrical Effort: H = (32*3) / 10 = 9.6 Branching Effort: B = 8  If we neglect logical effort (assume G = 1) Path Effort: F = GBH = 76.8 Number of Stages: N = log4F = 3.1  Try a 3-stage design
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 28 Gate Sizes & Delay Logical Effort: G = 1 * 6/3 * 1 = 2 Path Effort: F = GBH = 154 Stage Effort: Path Delay: Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7 A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0] word[0] word[15] 96 units of wordline capacitance 10 10 10 10 10 10 10 10 y z y z 1/3 ˆ 5.36 f F   ˆ 3 1 4 1 22.1 D f     
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 29 Comparison  Compare many alternatives with a spreadsheet  D = N(76.8 G)1/N + P Design N G P D NOR4 1 3 4 234 NAND4-INV 2 2 5 29.8 NAND2-NOR2 2 20/9 4 30.1 INV-NAND4-INV 3 2 6 22.1 NAND4-INV-INV-INV 4 2 7 21.1 NAND2-NOR2-INV-INV 4 20/9 6 20.5 NAND2-INV-NAND2-INV 4 16/9 6 19.7 INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4 NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 30 Review of Definitions Term Stage Path number of stages logical effort electrical effort branching effort effort effort delay parasitic delay delay i G g  out-path in-path C C H  N i B b  F GBH  F i D f  i P p  i F D d D P     out in C C h  on-path off-path on-path C C C b   f gh  f p d f p   g 1
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 31 Method of Logical Effort 1) Compute path effort 2) Estimate best number of stages 3) Sketch path with N stages 4) Estimate least delay 5) Determine best stage effort 6) Find gate sizes F GBH  4 log N F  1 N D NF P   1 ˆ N f F  ˆ i i i out in g C C f 
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 32 Limits of Logical Effort  Chicken and egg problem – Need path to compute G – But don’t know number of stages without G  Simplistic delay model – Neglects input rise time effects  Interconnect – Iteration required in designs with wire  Maximum speed only – Not minimum area/power for constrained delay
CMOS VLSI Design CMOS VLSI Design 4th Ed. 6: Logical Effort 33 Summary  Logical effort is useful for thinking of delay in circuits – Numeric logical effort characterizes gates – NANDs are faster than NORs in CMOS – Paths are fastest when effort delays are ~4 – Path delay is weakly sensitive to stages, sizes – But using fewer stages doesn’t mean faster paths – Delay of path is about log4F FO4 inverter delays – Inverters and NAND2 best for driving large caps  Provides language for discussing fast circuits – But requires practice to master

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Logical Effort in VLSI design and testing

  • 1.
  • 2.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 2 Outline  Logical Effort  Delay in a Logic Gate  Multistage Logic Networks  Choosing the Best Number of Stages  Example  Summary
  • 3.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 3 Introduction  Chip designers face a bewildering array of choices – What is the best circuit topology for a function? – How many stages of logic give least delay? – How wide should the transistors be?  Logical effort is a method to make these decisions – Uses a simple model of delay – Allows back-of-the-envelope calculations – Helps make rapid comparisons between alternatives – Emphasizes remarkable symmetries ? ? ?
  • 4.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 4 Example  Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file.  Decoder specifications: – 16 word register file – Each word is 32 bits wide – Each bit presents load of 3 unit-sized transistors – True and complementary address inputs A[3:0] – Each input may drive 10 unit-sized transistors  Ben needs to decide: – How many stages to use? – How large should each gate be? – How fast can decoder operate? A[3:0] A[3:0] 16 32 bits 16 words 4:16 Decoder Register File
  • 5.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 5 Delay in a Logic Gate  Express delays in process-independent unit  Delay has two components: d = f + p  f: effort delay = gh (a.k.a. stage effort) – Again has two components  g: logical effort – Measures relative ability of gate to deliver current – g  1 for inverter  h: electrical effort = Cout / Cin – Ratio of output to input capacitance – Sometimes called fanout  p: parasitic delay – Represents delay of gate driving no load – Set by internal parasitic capacitance abs d d   3RC  3 ps in 65 nm process 60 ps in 0.6 m process
  • 6.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 6 Electrical Effort: h = Cout / Cin Normalized Delay: d Inverter 2-input NAND g = 1 p = 1 d = h + 1 g = 4/3 p = 2 d = (4/3)h + 2 Effort Delay: f Parasitic Delay: p 0 1 2 3 4 5 0 1 2 3 4 5 6 Electrical Effort: h = Cout / Cin Normalized Delay: d Inverter 2-input NAND g = p = d = g = p = d = 0 1 2 3 4 5 0 1 2 3 4 5 6 Delay Plots d = f + p = gh + p  What about NOR2?
  • 7.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 7 Computing Logical Effort  DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.  Measure from delay vs. fanout plots  Or estimate by counting transistor widths A Y A B Y A B Y 1 2 1 1 2 2 2 2 4 4 Cin = 3 g = 3/3 Cin = 4 g = 4/3 Cin = 5 g = 5/3
  • 8.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 8 Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 4/3 5/3 6/3 (n+2)/3 NOR 5/3 7/3 9/3 (2n+1)/3 Tristate / mux 2 2 2 2 2 XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8  Logical effort of common gates
  • 9.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 9 Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 2 3 4 n NOR 2 3 4 n Tristate / mux 2 4 6 8 2n XOR, XNOR 4 6 8  Parasitic delay of common gates – In multiples of pinv (1)
  • 10.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 10 Example: Ring Oscillator  Estimate the frequency of an N-stage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay: d = 2 Frequency: fosc = 1/(2*N*d) = 1/4N 31 stage ring oscillator in 0.6 m process has frequency of ~ 200 MHz
  • 11.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 11 Example: FO4 Inverter  Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay: d = 5 d The FO4 delay is about 300 ps in 0.6 m process 15 ps in a 65 nm process
  • 12.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 12 Multistage Logic Networks  Logical effort generalizes to multistage networks  Path Logical Effort  Path Electrical Effort  Path Effort i G g  out-path in-path C H C  i i i F f g h     10 x y z 20 g1 = 1 h1 =x/10 g2 =5/3 h2 =y/x g3 =4/3 h3 =z/y g4 = 1 h4 =20/z
  • 13.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 13 Multistage Logic Networks  Logical effort generalizes to multistage networks  Path Logical Effort  Path Electrical Effort  Path Effort  Can we write F = GH? i G g  out path in path C H C    i i i F f g h    
  • 14.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 14 Paths that Branch  No! Consider paths that branch: G = 1 H = 90 / 5 = 18 GH = 18 h1 = (15 +15) / 5 = 6 h2 = 90 / 15 = 6 F = g1g2h1h2 = 36 = 2GH 5 15 15 90 90
  • 15.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 15 Branching Effort  Introduce branching effort – Accounts for branching between stages in path  Now we compute the path effort – F = GBH on path off path on path C C b C   i B b  i h BH   Note:
  • 16.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 16 Multistage Delays  Path Effort Delay  Path Parasitic Delay  Path Delay F i D f  i P p  i F D d D P    
  • 17.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 17 Designing Fast Circuits  Delay is smallest when each stage bears same effort  Thus minimum delay of N stage path is  This is a key result of logical effort – Find fastest possible delay – Doesn’t require calculating gate sizes i F D d D P     1 ˆ N i i f g h F   1 N D NF P  
  • 18.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 18 Gate Sizes  How wide should the gates be for least delay?  Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives.  Check work by verifying input cap spec is met. ˆ ˆ out in i i C C i out in f gh g g C C f    
  • 19.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 19 Example: 3-stage path  Select gate sizes x and y for least delay from A to B 8 x x x y y 45 45 A B
  • 20.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 20 Example: 3-stage path Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = 45/8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 Best Stage Effort Parasitic Delay P = 2 + 3 + 2 = 7 Delay D = 3*5 + 7 = 22 = 4.4 FO4 8 x x x y y 45 45 A B 3 ˆ 5 f F  
  • 21.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 21 Example: 3-stage path  Work backward for sizes y = 45 * (5/3) / 5 = 15 x = (15*2) * (5/3) / 5 = 10 P: 4 N: 4 45 45 A B P: 4 N: 6 P: 12 N: 3 8 x x x y y 45 45 A B
  • 22.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 22 Best Number of Stages  How many stages should a path use? – Minimizing number of stages is not always fastest  Example: drive 64-bit datapath with unit inverter D = NF1/N + P = N(64)1/N + N 1 1 1 1 8 4 16 8 2.8 23 64 64 64 64 Initial Driver Datapath Load N: f: D: 1 64 65 2 8 18 3 4 15 4 2.8 15.3 Fastest
  • 23.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 23 Derivation  Consider adding inverters to end of path – How many give least delay?  Define best stage effort N - n1 ExtraInverters Logic Block: n1 Stages Path EffortF   1 1 1 1 N n i inv i D NF p N n p       1 1 1 ln 0 N N N inv D F F F p N         1 ln 0 inv p      1 N F  
  • 24.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 24 Best Stage Effort  has no closed-form solution  Neglecting parasitics (pinv = 0), we find  = 2.718 (e)  For pinv = 1, solve numerically for  = 3.59   1 ln 0 inv p     
  • 25.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 25 Sensitivity Analysis  How sensitive is delay to using exactly the best number of stages?  2.4 <  < 6 gives delay within 15% of optimal – We can be sloppy! – I like  = 4 1.0 1.2 1.4 1.6 1.0 2.0 0.5 1.4 0.7 N / N 1.15 1.26 1.51 ( =2.4) (=6) D(N) /D(N) 0.0
  • 26.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 26 Example, Revisited  Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file.  Decoder specifications: – 16 word register file – Each word is 32 bits wide – Each bit presents load of 3 unit-sized transistors – True and complementary address inputs A[3:0] – Each input may drive 10 unit-sized transistors  Ben needs to decide: – How many stages to use? – How large should each gate be? – How fast can decoder operate? A[3:0] A[3:0] 16 32 bits 16 words 4:16 Decoder Register File
  • 27.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 27 Number of Stages  Decoder effort is mainly electrical and branching Electrical Effort: H = (32*3) / 10 = 9.6 Branching Effort: B = 8  If we neglect logical effort (assume G = 1) Path Effort: F = GBH = 76.8 Number of Stages: N = log4F = 3.1  Try a 3-stage design
  • 28.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 28 Gate Sizes & Delay Logical Effort: G = 1 * 6/3 * 1 = 2 Path Effort: F = GBH = 154 Stage Effort: Path Delay: Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7 A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0] word[0] word[15] 96 units of wordline capacitance 10 10 10 10 10 10 10 10 y z y z 1/3 ˆ 5.36 f F   ˆ 3 1 4 1 22.1 D f     
  • 29.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 29 Comparison  Compare many alternatives with a spreadsheet  D = N(76.8 G)1/N + P Design N G P D NOR4 1 3 4 234 NAND4-INV 2 2 5 29.8 NAND2-NOR2 2 20/9 4 30.1 INV-NAND4-INV 3 2 6 22.1 NAND4-INV-INV-INV 4 2 7 21.1 NAND2-NOR2-INV-INV 4 20/9 6 20.5 NAND2-INV-NAND2-INV 4 16/9 6 19.7 INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4 NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6
  • 30.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 30 Review of Definitions Term Stage Path number of stages logical effort electrical effort branching effort effort effort delay parasitic delay delay i G g  out-path in-path C C H  N i B b  F GBH  F i D f  i P p  i F D d D P     out in C C h  on-path off-path on-path C C C b   f gh  f p d f p   g 1
  • 31.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 31 Method of Logical Effort 1) Compute path effort 2) Estimate best number of stages 3) Sketch path with N stages 4) Estimate least delay 5) Determine best stage effort 6) Find gate sizes F GBH  4 log N F  1 N D NF P   1 ˆ N f F  ˆ i i i out in g C C f 
  • 32.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 32 Limits of Logical Effort  Chicken and egg problem – Need path to compute G – But don’t know number of stages without G  Simplistic delay model – Neglects input rise time effects  Interconnect – Iteration required in designs with wire  Maximum speed only – Not minimum area/power for constrained delay
  • 33.
    CMOS VLSI Design CMOSVLSI Design 4th Ed. 6: Logical Effort 33 Summary  Logical effort is useful for thinking of delay in circuits – Numeric logical effort characterizes gates – NANDs are faster than NORs in CMOS – Paths are fastest when effort delays are ~4 – Path delay is weakly sensitive to stages, sizes – But using fewer stages doesn’t mean faster paths – Delay of path is about log4F FO4 inverter delays – Inverters and NAND2 best for driving large caps  Provides language for discussing fast circuits – But requires practice to master