Lect 7: Verilog Behavioral model for Absolute Beginners

Digital Design Using Verilog
- For Absolute Beginners
LEC 7 :Verilog Behavioral Model

Introduction
• This model is considered as the highest level of
abstraction in the Verilog design modelling methods.
•It is also popularly known as Procedural assignment.
•Verilog behavioral model procedural statements
control the simulation and manipulate variables of the
data types .
•This behavioral model provides a wide scope for the
designer to build any complex design which can be
properly simulated and synthesized.

contd
• These statements are contained within procedures.
Each procedure has an activity flow associated with
it.
•The procedural block of Verilog HDL is defined as “a
region of code containing sequential statements.
•There are two types of procedural blocks.
(i).The always block & (ii).The initial block
• Each initial construct and each always construct
starts a separate activity flow.
• All of the activity flows are concurrent to model
the inherent concurrence of hardware.

Procedural assignments
• Procedural assignments are used for updating reg, integer,
time, real, realtime,and memory data types.
• There is a significant difference between procedural
assignments and continuous assignments:
Continuous assignments drive nets and are evaluated and
updated whenever an input operand
changes its value.
Procedural assignments update the value of variables under
the control of the procedural flow constructs
that surround them.

The always Block
• The ‘always’ block is a continuous loop that never
terminates.
• A Verilog module can contain any number of ‘always’
blocks and all these blocks are executed concurrently.
• The basic syntax of always block is
always @ (sensitivity list)
begin
statement 1
------------
statement n
end

contd
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• The sequential statements are executed if and if only
,the signals of the sensitivity list changes .
• The LHS of the statements in ‘always ‘ block is reg
type only.
• Ex: let us consider an example code.
module my-mux(A,B,S,Q,Q_b);
input A,B,S;
output Q,Q_b;
reg Q,Q_b;

always @(A or B or S)
begin
if(S)
Q = A; // procedural descriptions
else Q = B;
end
assign Q = ~Q_b; // continuous assignment
endmodule
contd

The Initial Block
• The initial block is typically used to write test bench
for simulation.
• It specifies the stimulus to be applied to the DUT.
• The initial block is executed only once at the
beginning of the simulation used in the test bench.

Illustration
• module behave;
[1:0] a, b;
initial begin
a = 1’b1;
b = 1’b0;
end
always begin
#50 a = ~a;
end
always begin
#100 b = ~b;
end
endmodule
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9
yayavaram@yahoo.com

contd
• In this model, the reg variables a and b initialize to 1
and 0 respectively at simulation time zero.
• The initial construct is then complete and does not
execute again during this simulation run.
• This initial construct contains a begin-end block
(also called a sequential block) of statements. In this
begin-end block a is initialized first, followed by b.
• The always constructs also start at time zero

contd
• But the values of the variables do not change until
the times specified by the delay controls (introduced
by #) have elapsed.
• Thus, reg a inverts after 50 time units and reg b
inverts after 100 time units.
• Since the always constructs repeat, this model will
produce two square waves.
• The reg a toggles with a period of 100 time units,
and reg b toggles with a period of 200 time units.
• The two always constructs proceed concurrently
throughout the entire simulation run.

Different Sequential Statements
(i).begin
sequential statements
end
Note: If there is a single statement in the block ‘begin’
and ‘end ‘ not required
(ii).if(expression)
Sequential statement
else

contd
• (iii).case(expression)
expr1 : Sequential statement 1
………..
expr n : Sequential statement n
default : Sequential statement
endcase
• (iv).forever
Sequential statemet

• (v). Repeat(expression)
• (vi). while(expression)
• (vii). for (expr1:expr2:expr3)
Sequential expression
• (viii).@(event_expression)
This makes a block of statements suspend until
event expression triggers.

Ex: Sequential Logic (D-F/F)
• module ex_Dff(D,clk,Q,Qb);
input D,clk ;
output Q,Qb;
reg Q, Qb ;
always @(negedge clk)
begin
Q = D;
Qb = ~D;
end
endmodule

Ex: 4 Bit ALU
• module ex_ALU4(Y,A,B,S);
input [3:0]A,B;
input [1:0] S ;
output [3:0] Y;
Parameter ADD=2’b00, SUB =2’b01, MUL = 2’10,
DIV = 2’b11;
always @(A or B or S)
case (S)
ADD : Y = A+B;

contd
SUB : Y = A-B ;
MUL : Y=A * B ;
DIV : Y = A/B;
endcase
endmodule

Lect 7: Verilog Behavioral model for Absolute Beginners

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